Electronic devices incorporating integrated circuits, such as application specific integrated circuits (ASICs), often employ power saving techniques to reduce power consumption and thereby achieve extended battery life. Small, portable devices such as mobile telephones and personal digital assistants (PDAs), for example, typically incorporate circuitry for implementing inactive modes to limit power consumption by logic circuitry. Inactive modes may include stand-by, low power and sleep modes.
Power dissipation in digital circuits, and more specifically in Complementary Metal Oxide Semiconductor (CMOS) circuits, is approximately proportional to the square of the supply voltage. Therefore, an effective way to achieve low-power performance is to scale down the supply voltage. CMOS circuits on ASICs are capable of operating at significantly reduced power levels. In order to avoid increases in propagation delay, however, the threshold voltage of the CMOS devices also is reduced.
The reduction in threshold voltage generally causes an increase in stand-by current due to changes in the sub-threshold leakage current of Metal Oxide Semiconductor (MOS) devices. The leakage current that flows through an “off” transistor tends to increase exponentially as the threshold voltage of a device is reduced. Therefore, electronic devices such as mobile telephones and PDAs that remain in an inactive mode for an extended period of time can exhibit significant leakage current, and cause undesirable drain on battery power during the inactive mode.
In order to reduce leakage current during stand-by modes, some ASICs include headswitches or footswitches that are electrically connected between the low voltage threshold (LVT) logic gates of a CMOS circuit and the power rail or ground rail. A headswitch is a high voltage threshold (HVT) Positive Channel Metal Oxide Semiconductor transistor positioned between the local power mesh routing of an ASIC core or block and the top-level power mesh routing. A footswitch is an HVT NMOS transistor positioned between the local ground mesh routing and the top-level ground rail/mesh.
During an inactive mode, the headswitches or footswitches are turned off to disconnect the LVT logic gates from the power/ground supply and thereby “collapse” the power rail. Because the headswitch or footswitch has a high threshold voltage, the amount of leakage current drawn from the power supply by the headswitch or footswitch is substantially reduced relative to the leakage current that would otherwise flow through the LVT logic gates. During an active mode, the headswitches or footswitches are turned on to connect the power supply and ground to the LVT gates. Therefore, during an active mode, the LVT logic gates are powered by substantially the same voltage as if they were directly connected to the power supply and ground.
The implementation of headswitch or footswitch circuitry on a global basis to collapse the power rail for a large array of logic cells can be relatively complicated. Conventional approaches to headswitch/footswitch implementation have relied on special routing and custom analysis and design tools. Numerous issues, including extra power routing to feed the headswitches and footswitches, significant area overhead, unmanageable IR voltage drops, signal routing accommodations, complications to standard tool flow and methodology, and the use of feed-throughs, further compound the complexity of conventional headswitch and footswitch implementations.